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? semiconductor components industries, llc, 2013 january, 2013 ? rev. 2 1 publication order number: ncp6121/d ncp6121 dual output 3 phase +1/0 phase controller with single svid interface for desktop and notebook cpu applications the ncp6121 dual output three plus one phase buck solution is optimized for intel vr12 compatible cpus. the controller combines true differential voltage sensing, differential inductor dcr current sensing, input voltage feed ? forward, and adaptive voltage positioning to provide accurately regulated power for desktop applications. the control system is based on dual ? edge pulse ? width modulation (pwm) combined with dcr current sensing providing the fastest initial response to dynamic load events and reduced system cost. it also sheds to single phase during light load operation and can auto frequency scale in light load while maintaining excellent transient performance. dual high performance operational error amplifiers are provided to simplify compensation of the system. patented dynamic reference injection further simplifies loop compensation by eliminating the need to compromise between closed ? loop transient response and dynamic vid performance. patented total current summing provides highly accurate current monitoring for droop and digital current monitoring. features ? meets intel vr12 and imvp7 specifications ? current mode dual edge modulation for fastest initial response to transient loading ? dual high performance operational error amplifier ? one digital soft start ramp for both rails ? dynamic reference injection ? accurate total summing current amplifier ? dac with droop feed ? forward injection ? dual high impedance differential voltage and total current sense amplifiers ? phase ? to ? phase dynamic current balancing ? ?lossless? dcr current sensing for current balancing ? summed thermally compensated inductor current sensing for droop ? true differential current balancing sense amplifiers for each phase ? adaptive voltage positioning (avp) ? switching frequency range of 200 khz ? 1.0 mhz ? startup into pre ? charged loads while avoiding false ovp ? power saving phase shedding ? vin feed forward ramp slope ? pin programming for internal svid parameters ? over voltage protection (ovp) and under voltage protection (uvp) ? over current protection (ocp) ? dual power good output with internal delays ? these devices are pb ? free and are rohs compliant applications ? desktop and notebook processors marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 27 of this data sheet. ordering information 52 1 qfn ? 52 case 485be a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package ncp6121 awlyywwg
ncp6121 http://onsemi.com 2 block diagram for ncp6121 figure 1. block diagram
ncp6121 http://onsemi.com 3 ncp6121, qfn52 single row pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 pin 1 indicator ncp6121 figure 2. pinout (top view) vsp tsense vrhot# sdio sclk alert# vr_rdy vr_rdya enable vcc rosc vrmp tsensea csn2 csp2 csn3 csp3 csn1 csp1 dron pwm1/addr pwm3/vboot pwm2 imax pwma/imaxa vboota diffout vsn trbst fb comp ilim droop cscomp cssum iout csref nc nc vsna vspa fba diffouta trbsta compa ilima droopa cscompa iouta cssuma cspa csna (not to scale) flag/gnd (pin 53) ncp6121 qfn52 single row pin descriptions pin no. symbol description 1 vsp non ? inverting input to the core differential remote sense amplifier. 2 tsense temp sense input for the multiphase converter 3 vr_hot# thermal logic output for over temperature. 4 sdio serial vid data interface. 5 sclk serial vid clock. 6 alert# serial vid alert#. 7 vr_rdy open drain output. high indicates that the core output is regulating. 8 vr_rdya open drain output. high indicates that the aux output is regulating. 9 enable logic input. logic high enables both outputs and logic low disables both outputs. 10 vcc power for the internal control circuits. a decoupling capacitor is connected from this pin to ground. 11 rosc a resistance from this pin to ground programs the oscillator frequency. this pin supplies a trimmed output voltage of 2 v. 12 vrmp feed ? forward input of vin for the ramp slope compensation. the current fed into this pin is used to control the ramp of pwm slope 13 tsensea temp sense input for the single phase converter 14 vsna inverting input to the aux differential remote sense amplifier 15 vspa non ? inverting input to the aux differential remote sense amplifier
ncp6121 http://onsemi.com 4 ncp6121 qfn52 single row pin descriptions pin no. description symbol 16 fba error amplifier voltage feedback for aux output 17 diffouta output of the aux differential remote sense amplifier 18 trbsta compensation pin for aux rail load transient boost. 19 compa output of the aux error amplifier and the inverting input of the pwm comparator for aux output 20 ilima over current shutdown threshold setting for aux output. a resistor to cscompa sets the threshold. 21 droopa used to program droop function for aux output. it?s connected to the resistor divider placed between cscompa and csrefa. 22 cscompa output of total current sense amplifier for aux output 23 iouta total output current monitor for aux output 24 cssuma inverting input of total current sense amplifier for aux output 25 cspa non ? inverting input to aux current sense amplifier 26 csna inverting input to aux current sense amplifier 27 vboota vboota voltage input pin. set to adjust the aux boot ? up voltage 28 pwma / imaxa aux pwm output to gate driver. also as icc_maxa input pin for aux rail. during start up it is used to pro- gram icc_maxa with a resistor to ground 29 imax icc_max input pin for core rail. during start up it is used to program icc_max with a resistor to ground 30* pwm2 phase 2 pwm output only. pull to v cc will configure as 2 ? phase operation. 31 pwm3 / vboot phase 3 pwm output. also as vboot input pin to adjust the core rail boot ? up voltage. during start up it is used to program vboot with a resistor to ground. 32 pwm1 / addr phase 1 pwm output. also as address program pin. a resistor to ground on this pin programs the svid address of the device. 33 dron bidirectional gate drive enable for core output. 34 csp1 non ? inverting input to current balance sense amplifier for phase 1 35 csn1 inverting input to current balance sense amplifier for phase 1 36 csp3 non ? inverting input to current balance sense amplifier for phase 3 37 csn3 inverting input to current balance sense amplifier for phase 3 38 csp2 non ? inverting input to current balance sense amplifier for phase 2 39* csn2 inverting input to current balance sense amplifier for phase 2 40 nc no connection 41 nc no connection 42 csref total output current sense amplifier reference voltage input. 43 iout total output current monitor for core output. 44 cssum inverting input of total current sense amplifier for core output. 45 cscomp output of total current sense amplifier for core output. 46 droop used to program droop function for core output. it?s connected to the resistor divider placed between cscomp and csref summing node. 47 ilim over current shutdown threshold setting for core output. resistor to cscomp to set threshold. 48 comp output of the error amplifier and the inverting inputs of the pwm comparators for the core output. 49 fb error amplifier voltage feedback for core output 50 trbst compensation pin for core rail load transient boost. 51 vsn inverting input to the core differential remote sense amplifier. 52 diffout output of the core differential remote sense amplifier. 53 flag / gnd power supply return (qfn flag)
ncp6121 http://onsemi.com 5 absolute maximum ratings electrical information pin symbol v max v min unit comp,compa vcc + 0.3 v ? 0.3 v v cscomp, cscompa vcc + 0.3 v ? 0.3 v v vsn gnd + 300 mv gnd ? 300 mv mv diffout, diffouta vcc + 0.3 v ? 0.3 v v vr_rdy,vr_rdya vcc + 0.3 v ? 0.3 v v vcc 6.5 v ? 0.3 v v rosc vcc + 0.3 v ? 0.3 v v iout, iouta output 2.0 v ? 0.3 v v vrmp +25 v ? 0.3 v v all other pins vcc + 0.3v ? 0.3 v v **all signals referenced to gnd unless noted otherwise. thermal information pin symbol symbol typ unit thermal characteristic qfn package, (note 1) r ja 68 c/w operating junction temperature range, (note 2) t j ? 10 to 125 c operating ambient temperature range ? 10 to 100 c maximum storage temperature range t stg ? 40 to +150 c moisture sensitivity level qfn package msl 1 *the maximum package power dissipation must be observed. 1. jesd 51 ? 5 (1s2p direct ? attach method) with 0 lfm 2. jesd 51 ? 7 (1s2p direct ? attach method) with 0 lfm ncp6121 electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5 v; c vcc = 0.1 f parameter test conditions min typ max unit error amplifier input bias current @ 1.3 v ? 400 400 na open loop dc gain c l = 20 pf to gnd, r l = 10 k to gnd 80 db open loop unity gain bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 55 mhz slew rate v in = 100 mv, g = ? 10 v/v, v out = 1.5 v ? 2.5 v, c l = 20 pf to gnd, dc load = 10k to gnd 20 v/ s maximum output voltage i source = 2.0 ma 3.5 ? ? v minimum output voltage i sink = 2.0 ma ? ? 1 v differential summing amplifier input bias current vsp, vspa ,vsn, vsna = 1.3 v ? 400 ? 400 na vsp input voltage range ? 0.3 ? 3.0 v vsn input voltage range ? 0.3 ? 0.3 v
ncp6121 http://onsemi.com 6 ncp6121 electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5 v; c vcc = 0.1 f parameter unit max typ min test conditions differential summing amplifier ? 3 db bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 12 mhz closed loop dc gain vs+ to vs ? = 0.5 to 1.3 v 1.0 v/v droop accuracy csref ? droop = 80 mv dac = 0.8 v to 1.2 v ? 81.5 ? 78.5 mv current summing amplifier offset voltage (v os ), note 3 ? 300 300 uv input bias current cssum = cssuma = 1 v ? 7.5 7.5 na open loop gain 80 db current sense unity gain bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 10 mhz maximum cscomp (a) output voltage i source = 2 ma cssum(a) = cscomp(a) 3.5 ? ? v minimum cscomp(a) output voltage i sink = 2 ma cssum(a) = cscomp(a) ? ? 0.15 v current balance amplifier input bias current csp 1 ? 3 = csn 1 ? 3 = 1.2 v cspa = csna = 1.2 v ? 50 ? 100 ? 50 100 na common mode input voltage range cspx = csnx 0 ? 2.0 v differential mode input voltage range csnx = 1.2 v ? 100 ? 100 mv input offset voltage matching cspx = csnx = 1.2 v, measured from the average ? 1.5 ? 1.5 mv current sense amplifier gain 0 v < cspx ? csnx < 0.1v 5.7 6.0 6.3 v/v multiphase current sense gain matching 10 mv < csnx = cspx < 30m v ? 3 3 % ? 3 db bandwidth 8 mhz input supply supply voltage range 4.75 5.25 v vcc quiescent current en = high 38 43 ma en = low 5 ma uvlo threshold v cc rising 4.5 v v cc falling 4.1 v vcc uvlo hysteresis 160 mv dac slew rate soft start slew rate 2.5 mv/ s slew rate slow 5 mv/ s slew rate fast 20 mv/ s aux soft start slew rate 2.5 mv/ s aux slew rate slow 2.5 mv/ s aux slew rate fast 10 mv/ s enable input enable high input leakage current external 1k pull ? up to 3.3 v ? 1.0 a upper threshold v upper 0.8 v lower threshold v lower 0.3 v
ncp6121 http://onsemi.com 7 ncp6121 electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5 v; c vcc = 0.1 f parameter unit max typ min test conditions enable input total hysteresis v upper ? v lower 90 mv enable delay time measure time from enable transitioning hi to when dron goes high, v boot is not 0 v 5.0 ms drvon output high voltage sourcing 500 a 3.0 v output low voltage sinking 500 a 0.1 v rise/fall time c l (pcb) = 20 pf, vo = 10% to 90% 10 ns internal pull down resistance en = low 70 k iout / iouta output input referred offset voltage i limit to csref ? 1.5 1.5 mv output source current i limit sink current = 80 a 800 ua current gain (iout current ) / (i limitcurrent ), r ilim = 20k, r iout = 5.0k, dac = 0.8 v, 1.25 v, 1.52 v 9.5 10 10.5 oscillator switching frequency range 200 ? 1000 khz 3 phase operation r t = 6.98 k 360 400 440 khz r osc output voltage r t = 6.98 k 1.95 2.00 2.05 v output over voltage and under voltage protection (ovp & uvp) absolute over voltage threshold during soft start csref, csna 1.9 2.0 2.1 v over voltage threshold above dac vsp(a) rising, dac = 1.2 v and 1.52 v 150 175 200 mv over voltage delay vsp(a) rising to pwmx low 50 ns under voltage threshold below dac vsp(a) falling, (dac = 1.2 v & 1.52 v) 250 300 350 mv under ? voltage delay 5 s vr12 dac system voltage accuracy 1.0 v dac < 1.52 v 0.8v< dac < 0.995 v 0.25v < dac < 0.795 v ? 0.5 ? 5 ? 8 0.5 5 8 % mv mv droop feed ? forward up current droop feed ? forward down current measured on droop, droopa measured on droop, droopa 58 19 65 25 72 31 a droop feed ? forward pulse on ? time 0.16 s overcurrent protection (core rail) ilim threshold current (ocp shutdown after 50 s delay) (ps0) r lim = 20k 9.0 10 11.0 a ilim threshold current (immediate ocp shutdown) (ps0) r lim = 20k 13.5 15 16.5 a ilim threshold current (ocp shutdown after 50 s delay) (ps1, ps2, ps3) r lim = 20k, n = number of phases in ps0 mode 10/n a ilim threshold current (immediate ocp shutdown) (ps1, ps2, ps3) r lim = 20k, n = number of phases in ps0 mode 15/n a overcurrent protection (+1 rail)
ncp6121 http://onsemi.com 8 ncp6121 electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5 v; c vcc = 0.1 f parameter unit max typ min test conditions overcurrent protection (+1 rail) ilim threshold current (ocp shutdown after 50 s delay) (ps0) r lim = 20k 8.5 10 11.5 a ilim threshold current (immediate ocp shutdown) (ps0) r lim = 20k 13.5 15 16.5 a ilim threshold current (ocp shutdown after 50 s delay) (ps1, ps2, ps3) r lim = 20k, n = phase number in ps0 mode 10 a ilim threshold current (immediate ocp shutdown) (ps1, ps2, ps3) r lim = 20k, n = phase number in ps0 mode 15 a modulators (pwm comparators) for core and aux 0% duty cycle comp voltage when the pwm outputs remain lo 1.3 ? v 100% duty cycle comp voltage when the pwm outputs remain hi v rmp = 12.0 v ? 2.5 ? v pwm ramp duty cycle matching comp = 2 v, pwm t on matching 1 % pwm phase angle error between adjacent phases ? 15 15 ramp feed ? forward voltage range 5 20 v trbst trbst/comp offset trbst starts sinking current 350 mv trbst sink capability 500 a trbsta trbsta/compa offset trbst starts sinking current 350 mv trbsta sink capability 500 a vr_hot# output low voltage i _vrhot = ? 4 ma 0.3 v output leakage current high impedance state ? 1.0 ? 1.0 a tsense/tsensea alert# assert threshold 513 mv alert# de ? assert threshold 491 mv vrhot assert threshold 472 mv vrhot rising threshold 494 mv tsense bias current 116 120 124 a adc voltage range 0 2 v total unadjusted error (tue) ? 1 +1 % differential non ? linearity (dnl) 8 ? bit 1 lsb power supply sensitivity +/ ? 1 % conversion time 30 s round robin 90 s vr_rdy, vr_rdya (power good) output output low saturation voltage i vr_rdy(a) = 4 ma ? ? 0.3 v rise time external pull ? up o f 1 k to 3.3 v , c tot = 45 pf, vo = 10% to 90% ? 100 ns
ncp6121 http://onsemi.com 9 ncp6121 electrical characteristics unless otherwise stated: ? 10 c < t a < 100 c; v cc = 5 v; c vcc = 0.1 f parameter unit max typ min test conditions vr_rdy, vr_rdya (power good) output fall time external pull ? up of 1 k to 3.3 v, c tot = 45 pf, vo = 90% to 10% 10 ns output voltage at power ? up vr_rdy, vr_rdya pulled up to 5 v via 2 k ? ? 1.0 v output leakage current when high vr_rdy and vr_rdya = 5.0 v ? 1.0 ? 1.0 a vr_rdy delay (rising) dac = target to vr_rdy 500 s vr_rdy delay (falling) from ocp or ovp ? 5 ? s pwm outputs output high voltage sourcing 500 a v cc ? 0.2 v ? ? v output mid voltage no load, setps = 02 1.9 2.0 2.1 v output low voltage sinking 500 a ? ? 0.7 v rise and fall time c l (pcb) = 50 pf, vo = gnd to v cc ? 10 ns 2/3 phase detection pwm pin source current 100 a pwm pin threshold voltage 3.3 v phase detect timer 20 s sclk, sdio v il input low voltage .45 v v ih input high voltage 0.65 v v oh output high voltage 1.05 v r on buffer on resistance (data line, alert#, and vrhot) 4 13 leakage current sdio, slck, alert ? 100 100 a pad capacitance, (note 3) 4.0 pf vr clock to data delay (t co ), (note 3) 4 8.3 ns setup time (t su ), (note 3) 7 ns hold time (t hld ), (note 3) 14 ns 3. guaranteed by design or characterization data, not in production test; table 1. vr12 vid codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage (v) hex 0 0 0 0 0 0 0 0 off 00 0 0 0 0 0 0 0 1 0.25000 01 0 0 0 0 0 0 1 0 0.25500 02 0 0 0 0 0 0 1 1 0.26000 03 0 0 0 0 0 1 0 0 0.26500 04 0 0 0 0 0 1 0 1 0.27000 05 0 0 0 0 0 1 1 0 0.27500 06 0 0 0 0 0 1 1 1 0.28000 07 0 0 0 0 1 0 0 0 0.28500 08
ncp6121 http://onsemi.com 10 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 0 0 0 1 0 0 1 0.29000 09 0 0 0 0 1 0 1 0 0.29500 0a 0 0 0 0 1 0 1 1 0.30000 0b 0 0 0 0 1 1 0 0 0.30500 0c 0 0 0 0 1 1 0 1 0.31000 0d 0 0 0 0 1 1 1 0 0.31500 0e 0 0 0 0 1 1 1 1 0.32000 0f 0 0 0 1 0 0 0 0 0.32500 10 0 0 0 1 0 0 0 1 0.33000 11 0 0 0 1 0 0 1 0 0.33500 12 0 0 0 1 0 0 1 1 0.34000 13 0 0 0 1 0 1 0 0 0.34500 14 0 0 0 1 0 1 0 1 0.35000 15 0 0 0 1 0 1 1 0 0.35500 16 0 0 0 1 0 1 1 1 0.36000 17 0 0 0 1 1 0 0 0 0.36500 18 0 0 0 1 1 0 0 1 0.37000 19 0 0 0 1 1 0 1 0 0.37500 1a 0 0 0 1 1 0 1 1 0.38000 1b 0 0 0 1 1 1 0 0 0.38500 1c 0 0 0 1 1 1 0 1 0.39000 1d 0 0 0 1 1 1 1 0 0.39500 1e 0 0 0 1 1 1 1 1 0.40000 1f 0 0 1 0 0 0 0 0 0.40500 20 0 0 1 0 0 0 0 1 0.41000 21 0 0 1 0 0 0 1 0 0.41500 22 0 0 1 0 0 0 1 1 0.42000 23 0 0 1 0 0 1 0 0 0.42500 24 0 0 1 0 0 1 0 1 0.43000 25 0 0 1 0 0 1 1 0 0.43500 26 0 0 1 0 0 1 1 1 0.44000 27 0 0 1 0 1 0 0 0 0.44500 28 0 0 1 0 1 0 0 1 0.45000 29 0 0 1 0 1 0 1 0 0.45500 2a 0 0 1 0 1 0 1 1 0.46000 2b 0 0 1 0 1 1 0 0 0.46500 2c 0 0 1 0 1 1 0 1 0.47000 2d 0 0 1 0 1 1 1 0 0.47500 2e 0 0 1 0 1 1 1 1 0.48000 2f 0 0 1 1 0 0 0 0 0.48500 30 0 0 1 1 0 0 0 1 0.49000 31
ncp6121 http://onsemi.com 11 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 0 1 1 0 0 1 0 0.49500 32 0 0 1 1 0 0 1 1 0.50000 33 0 0 1 1 0 1 0 0 0.50500 34 0 0 1 1 0 1 0 1 0.51000 35 0 0 1 1 0 1 1 0 0.51500 36 0 0 1 1 0 1 1 1 0.52000 37 0 0 1 1 1 0 0 0 0.52500 38 0 0 1 1 1 0 0 1 0.53000 39 0 0 1 1 1 0 1 0 0.53500 3a 0 0 1 1 1 0 1 1 0.54000 3b 0 0 1 1 1 1 0 0 0.54500 3c 0 0 1 1 1 1 0 1 0.55000 3d 0 0 1 1 1 1 1 0 0.55500 3e 0 0 1 1 1 1 1 1 0.56000 3f 0 1 0 0 0 0 0 0 0.56500 40 0 1 0 0 0 0 0 1 0.57000 41 0 1 0 0 0 0 1 0 0.57500 42 0 1 0 0 0 0 1 1 0.58000 43 0 1 0 0 0 1 0 0 0.58500 44 0 1 0 0 0 1 0 1 0.59000 45 0 1 0 0 0 1 1 0 0.59500 46 0 1 0 0 0 1 1 1 0.60000 47 0 1 0 0 1 0 0 0 0.60500 48 0 1 0 0 1 0 0 1 0.61000 49 0 1 0 0 1 0 1 0 0.61500 4a 0 1 0 0 1 0 1 1 0.62000 4b 0 1 0 0 1 1 0 0 0.62500 4c 0 1 0 0 1 1 0 1 0.63000 4d 0 1 0 0 1 1 1 0 0.63500 4e 0 1 0 0 1 1 1 1 0.64000 4f 0 1 0 1 0 0 0 0 0.64500 50 0 1 0 1 0 0 0 1 0.65000 51 0 1 0 1 0 0 1 0 0.65500 52 0 1 0 1 0 0 1 1 0.66000 53 0 1 0 1 0 1 0 0 0.66500 54 0 1 0 1 0 1 0 1 0.67000 55 0 1 0 1 0 1 1 0 0.67500 56 0 1 0 1 0 1 1 1 0.68000 57 0 1 0 1 1 0 0 0 0.68500 58 0 1 0 1 1 0 0 1 0.69000 59 0 1 0 1 1 0 1 0 0.69500 5a
ncp6121 http://onsemi.com 12 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 1 0 1 1 0 1 1 0.70000 5b 0 1 0 1 1 1 0 0 0.70500 5c 0 1 0 1 1 1 0 1 0.71000 5d 0 1 0 1 1 1 1 0 0.71500 5e 0 1 0 1 1 1 1 1 0.72000 5f 0 1 1 0 0 0 0 0 0.72500 60 0 1 1 0 0 0 0 1 0.73000 61 0 1 1 0 0 0 1 0 0.73500 62 0 1 1 0 0 0 1 1 0.74000 63 0 1 1 0 0 1 0 0 0.74500 64 0 1 1 0 0 1 0 1 0.75000 65 0 1 1 0 0 1 1 0 0.75500 66 0 1 1 0 0 1 1 1 0.76000 67 0 1 1 0 1 0 0 0 0.76500 68 0 1 1 0 1 0 0 1 0.77000 69 0 1 1 0 1 0 1 0 0.77500 6a 0 1 1 0 1 0 1 1 0.78000 6b 0 1 1 0 1 1 0 0 0.78500 6c 0 1 1 0 1 1 0 1 0.79000 6d 0 1 1 0 1 1 1 0 0.79500 6e 0 1 1 0 1 1 1 1 0.80000 6f 0 1 1 1 0 0 0 0 0.80500 70 0 1 1 1 0 0 0 1 0.81000 71 0 1 1 1 0 0 1 0 0.81500 72 0 1 1 1 0 0 1 1 0.82000 73 0 1 1 1 0 1 0 0 0.82500 74 0 1 1 1 0 1 0 1 0.83000 75 0 1 1 1 0 1 1 0 0.83500 76 0 1 1 1 0 1 1 1 0.84000 77 0 1 1 1 1 0 0 0 0.84500 78 0 1 1 1 1 0 0 1 0.85000 79 0 1 1 1 1 0 1 0 0.85500 7a 0 1 1 1 1 0 1 1 0.86000 7b 0 1 1 1 1 1 0 0 0.86500 7c 0 1 1 1 1 1 0 1 0.87000 7d 0 1 1 1 1 1 1 0 0.87500 7e 0 1 1 1 1 1 1 1 0.88000 7f 1 0 0 0 0 0 0 0 0.88500 80 1 0 0 0 0 0 0 1 0.89000 81 1 0 0 0 0 0 1 0 0.89500 82 1 0 0 0 0 0 1 1 0.90000 83
ncp6121 http://onsemi.com 13 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 0 0 0 0 1 0 0 0.90500 84 1 0 0 0 0 1 0 1 0.91000 85 1 0 0 0 0 1 1 0 0.91500 86 1 0 0 0 0 1 1 1 0.92000 87 1 0 0 0 1 0 0 0 0.92500 88 1 0 0 0 1 0 0 1 0.93000 89 1 0 0 0 1 0 1 0 0.93500 8a 1 0 0 0 1 0 1 1 0.94000 8b 1 0 0 0 1 1 0 0 0.94500 8c 1 0 0 0 1 1 0 1 0.95000 8d 1 0 0 0 1 1 1 0 0.95500 8e 1 0 0 0 1 1 1 1 0.96000 8f 1 0 0 1 0 0 0 0 0.96500 90 1 0 0 1 0 0 0 1 0.97000 91 1 0 0 1 0 0 1 0 0.97500 92 1 0 0 1 0 0 1 1 0.98000 93 1 0 0 1 0 1 0 0 0.98500 94 1 0 0 1 0 1 0 1 0.99000 95 1 0 0 1 0 1 1 0 0.99500 96 1 0 0 1 0 1 1 1 1.00000 97 1 0 0 1 1 0 0 0 1.00500 98 1 0 0 1 1 0 0 1 1.01000 99 1 0 0 1 1 0 1 0 1.01500 9a 1 0 0 1 1 0 1 1 1.02000 9b 1 0 0 1 1 1 0 0 1.02500 9c 1 0 0 1 1 1 0 1 1.03000 9d 1 0 0 1 1 1 1 0 1.03500 9e 1 0 0 1 1 1 1 1 1.04000 9f 1 0 1 0 0 0 0 0 1.04500 a0 1 0 1 0 0 0 0 1 1.05000 a1 1 0 1 0 0 0 1 0 1.05500 a2 1 0 1 0 0 0 1 1 1.06000 a3 1 0 1 0 0 1 0 0 1.06500 a4 1 0 1 0 0 1 0 1 1.07000 a5 1 0 1 0 0 1 1 0 1.07500 a6 1 0 1 0 0 1 1 1 1.08000 a7 1 0 1 0 1 0 0 0 1.08500 a8 1 0 1 0 1 0 0 1 1.09000 a9 1 0 1 0 1 0 1 0 1.09500 aa 1 0 1 0 1 0 1 1 1.10000 ab 1 0 1 0 1 1 0 0 1.10500 ac
ncp6121 http://onsemi.com 14 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 0 1 0 1 1 0 1 1.11000 ad 1 0 1 0 1 1 1 0 1.11500 ae 1 0 1 0 1 1 1 1 1.12000 af 1 0 1 1 0 0 0 0 1.12500 b0 1 0 1 1 0 0 0 1 1.13000 b1 1 0 1 1 0 0 1 0 1.13500 b2 1 0 1 1 0 0 1 1 1.14000 b3 1 0 1 1 0 1 0 0 1.14500 b4 1 0 1 1 0 1 0 1 1.15000 b5 1 0 1 1 0 1 1 0 1.15500 b6 1 0 1 1 0 1 1 1 1.16000 b7 1 0 1 1 1 0 0 0 1.16500 b8 1 0 1 1 1 0 0 1 1.17000 b9 1 0 1 1 1 0 1 0 1.17500 ba 1 0 1 1 1 0 1 1 1.18000 bb 1 0 1 1 1 1 0 0 1.18500 bc 1 0 1 1 1 1 0 1 1.19000 bd 1 0 1 1 1 1 1 0 1.19500 be 1 0 1 1 1 1 1 1 1.20000 bf 1 1 0 0 0 0 0 0 1.20500 c0 1 1 0 0 0 0 0 1 1.21000 c1 1 1 0 0 0 0 1 0 1.21500 c2 1 1 0 0 0 0 1 1 1.22000 c3 1 1 0 0 0 1 0 0 1.22500 c4 1 1 0 0 0 1 0 1 1.23000 c5 1 1 0 0 0 1 1 0 1.23500 c6 1 1 0 0 0 1 1 1 1.24000 c7 1 1 0 0 1 0 0 0 1.24500 c8 1 1 0 0 1 0 0 1 1.25000 c9 1 1 0 0 1 0 1 0 1.25500 ca 1 1 0 0 1 0 1 1 1.26000 cb 1 1 0 0 1 1 0 0 1.26500 cc 1 1 0 0 1 1 0 1 1.27000 cd 1 1 0 0 1 1 1 0 1.27500 ce 1 1 0 0 1 1 1 1 1.28000 cf 1 1 0 1 0 0 0 0 1.28500 d0 1 1 0 1 0 0 0 1 1.29000 d1 1 1 0 1 0 0 1 0 1.29500 d2 1 1 0 1 0 0 1 1 1.30000 d3 1 1 0 1 0 1 0 0 1.30500 d4 1 1 0 1 0 1 0 1 1.31000 d5
ncp6121 http://onsemi.com 15 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 1 0 1 0 1 1 0 1.31500 d6 1 1 0 1 0 1 1 1 1.32000 d7 1 1 0 1 1 0 0 0 1.32500 d8 1 1 0 1 1 0 0 1 1.33000 d9 1 1 0 1 1 0 1 0 1.33500 da 1 1 0 1 1 0 1 1 1.34000 db 1 1 0 1 1 1 0 0 1.34500 dc 1 1 0 1 1 1 0 1 1.35000 dd 1 1 0 1 1 1 1 0 1.35500 de 1 1 0 1 1 1 1 1 1.36000 df 1 1 1 0 0 0 0 0 1.36500 e0 1 1 1 0 0 0 0 1 1.37000 e1 1 1 1 0 0 0 1 0 1.37500 e2 1 1 1 0 0 0 1 1 1.38000 e3 1 1 1 0 0 1 0 0 1.38500 e4 1 1 1 0 0 1 0 1 1.39000 e5 1 1 1 0 0 1 1 0 1.39500 e6 1 1 1 0 0 1 1 1 1.40000 e7 1 1 1 0 1 0 0 0 1.40500 e8 1 1 1 0 1 0 0 1 1.41000 e9 1 1 1 0 1 0 1 0 1.41500 ea 1 1 1 0 1 0 1 1 1.42000 eb 1 1 1 0 1 1 0 0 1.42500 ec 1 1 1 0 1 1 0 1 1.43000 ed 1 1 1 0 1 1 1 0 1.43500 ee 1 1 1 0 1 1 1 1 1.44000 ef 1 1 1 1 0 0 0 0 1.44500 f0 1 1 1 1 0 0 0 1 1.45000 f1 1 1 1 1 0 0 1 0 1.45500 f2 1 1 1 1 0 0 1 1 1.46000 f3 1 1 1 1 0 1 0 0 1.46500 f4 1 1 1 1 0 1 0 1 1.47000 f5 1 1 1 1 0 1 1 0 1.47500 f6 1 1 1 1 0 1 1 1 1.48000 f7 1 1 1 1 1 0 0 0 1.48500 f8 1 1 1 1 1 0 0 1 1.49000 f9 1 1 1 1 1 0 1 0 1.49500 fa 1 1 1 1 1 0 1 1 1.50000 fb 1 1 1 1 1 1 0 0 1.50500 fc 1 1 1 1 1 1 0 1 1.51000 fd
ncp6121 http://onsemi.com 16 table 1. vr12 vid codes vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 1 1 1 1 1 1 1 0 1.51500 fe 1 1 1 1 1 1 1 1 1.52000 ff vr12_en sclk sdio vspa vid pkt vspa svid bus idle vsp vid pkt vsp svid alert vr_rdya vr_rdy status pkt 12v 5v figure 3. start ? up timing diagram sclk sdio t co _cpu t su t hld t co _cpu vr latch cpu send t co_cpu = clock to data delay in cpu tsu =0.5*t ? t co_cpu thld =0.5*t +t co_cpu cpu driving, single data rate sclk sdio t co_vr t su t hld cpu latch vr send t co_vr = clock to data delay in vr tsu =t ? 2*t fly ? t co_vr thld =2*t fly + t co_vr t fly propagation time on serial vid bus vr driving, single data rate figure 4. svid timing diagram
ncp6121 http://onsemi.com 17 table 2. state truth table state vr_rdy(a) pin error amp comp(a) pin ovp(a) and uvp(a) drvon pin method of reset por 0 < v cc < uvlo n/a n/a n/a resistive pull down disabled en < threshold uvlo >threshold low low disabled low start up delay & calibration en > threshold uvlo > threshold low low disabled low drvon fault en > threshold uvlo > threshold drvon < threshold low low disabled resistive pull up driver must release drvon to high soft ? start en > threshold uvlo >threshold drvon > high low operational active / no latch high normal operation en > threshold uvlo >threshold drvon > high high operational active / latching high n/a over voltage low n/a dac + 150 mv high over current low operational last dac code low vid code = 00h low: if reg34h:bit0 = 0; high:if reg34h:bit0 = 1; clamped disabled high, pwm outputs in low state
ncp6121 http://onsemi.com 18 controller por disable vcc > uvlo calibrate drive off phase detect soft start ramp normal vr _ rdy ovp uvp en = 1 3 . 5 ms and cal done vccp > uvlo and dron high en = 0 vs > ovp vdrp > ilim no _ cpu invalid vid vs < uvp vs > uvp dac = vid vcc < uvlo soft start ramp dac = vboot figure 5. state diagram
ncp6121 http://onsemi.com 19 general the ncp6121 is a dual output four/three phase plus one phase dual edge modulated multiphase pwm controller designed to meet the intel vr12 specifications with a serial svid control interface. the ncp6121 implements ps0, ps1, ps2 and ps3 power saving states. it is designed to work in notebook, desktop, and server applications. for core rail: power status pwm output operating mode ps0 multi ? phase pwm interleaving output ps1 single ? phase rpm ccm mode (pwm1 only, pwm2~3 stay in mid) ps2 single ? phase rpm dcm mode (pwm1 only, pwm2~3 stay in mid) ps3 existing definition is same as ps2 for aux rail: power status pwm output operating mode ps0 single ? phase rpm output ps1 single ? phase rpm ccm mode ps2 single ? phase rpm dcm mode ps3 existing definition is same as ps2 vid code change is supported by svid interface with three options as below: option svid command code feature register address (indicating the slew rate of vid code change) setvid_fast 01h > 10 mv/ s vid code change slew rate 24h setvid_slow 02h = 1/4 of setvid_fast vid code change slew rate 25h setvid_decay 03h no control, vid code down n/a serial vid the ncp6121 supports the intel serial vid interface. it communicates with the microprocessor through three wires (sclk, sdio, alert#). the table of supported registers is shown below. index name description access default 00h vendor id uniquely identifies the vr vendor. the vendor id assigned by intel to on semicon- ductor is 0x1ah r 0x1ah 01h product id uniquely identifies the vr product. the vr vendor assigns this number. r 0x51 02h product revision uniquely identifies the revision or stepping of the vr control ic. the vr vendor as- signs this data. r 0x0a 05h protocol id identifies the svid protocol the controller supports r 0x01 06h capability informs the master of the controller?s capabilities, 1 = supported, 0 = not supported bit 7 = iout_format. bit 7 = 0 when 1a = 1lsb of reg 15h. bit 7 = when reg 15 ffh = icc_max. default = 1 bit 6 = adc measurement of temp supported = 1 bit 5 = adc measurement of pin supported = 0 bit 4 = adc measurement of vin supported = 0 bit 3 = adc measurement of iin supported = 0 bit 2 = adc measurement of pout supported = 1 bit 1 = adc measurement of vout supported = 1 bit 0 = adc measurement of iout supported = 1 r 0xc7 07h generic id 51h or 31h, depending on the generic r 51h or 31h
ncp6121 http://onsemi.com 20 index default access description name 10h status_1 data register read after the alert# signal is asserted. conveying the status of the vr. r 00h 11h status_2 data register showing optional status_2 data. r 00h 12h temp zone data register showing temperature zones the system is operating in r 00h 15h i_out 8 bit binary word adc of current. this register reads 0xff when the output current is at icc_max r 01h 16h v_out 8 bit binary word adc of output voltage, measured between vsp and vsn. lsb size is 8 mv r 01h 17h vr_temp 8 bit binary word adc of voltage. binary format in deg c, ie 100c = 64h. a value of 00h indicates this function is not supported r 01h 18h p_out 8 bit binary word representative of output power. the output voltage is multiplied by the output current value and the result is stored in this register. a value of 00h indic- ates this function is not supported r 01h 1ch status 2 last read when the status 2 register is read its contents are copied into this register. the format is the same as the status 2 register. r 00h 21h icc_max data register containing the icc_max the platform supports. the value is measured on the iccmax pin on power up and placed in this register. from that point on the re- gister is read only. r 00h 22h temp_max data register containing the max temperature the platform supports and the level vr_hot asserts. this value defaults to 100 c and programmable over the svid inter- face r/w 64h 24h sr_fast slew rate for setvid_fast commands. binary format in mv/us. r 0ah 25h sr_slow slew rate for setvid_slow commands. it is 4x slower than the sr_fast rate. binary format in mv/us r 02h 26h vboot the vboot is programmed using resistors on the vboot pin which is sensed on power up. the controller will ramp to vboot and hold at vboot until it receives a new svid setvid command to move to a different voltage. default value = 0, i.e. this occurs if no resistor is connected to the vboot pin. in this case the controller will wait till it gets an svid command to set the output voltage., vr12 vid format, ie 97h = 1.0 v r 00h 30h vout_max programmed by master and sets the maximum vid the vr will support. if a higher vid code is received, the vr should respond with ?not supported? acknowledge. vr 12 vid format. rw fbh 31h vid setting data register containing currently programmed vid voltage. vid data format. rw 00h 32h pwr state register containing the current programmed power state. rw 00h 33h offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is sign bit, 0 = positive margin, 1 = negative margin. remaining 7 bits are # vid steps for margin 2s complement. 00h = no margin 01h = +1 vid step 02h = +2 vid steps ffh = ? 1 vid step feh = ? 2 vid steps. rw 00h 34h multivr config
ncp6121 http://onsemi.com 21 boot voltage programming the ncp6121 has a vboot voltage register that can be externally programmed for each output. the vboota also provides a feature that allows the ?+1? single phase output to be disabled and effectively removed from the svid bus. if the single phase output is disabled it alters the svid address setting table to allow the multi ? phase rail to show up at an even or odd address. see the boot voltage t able below. table 3. boot voltage table boot voltage (v) resistor value ( ) 0 10k 0.9 25k 1.0 45k 1.1 70k 1.2 95k 1.35 125k 1.5 165k vcc shutdown (vboota only) addressing programming the ncp6121 supports seven possible dual svid device addresses and eight possible single device addresses. pin 32 (pwm1/addr) is used to set the svid address. on power up a 10 a current is sourced from this pin through a resistor connected to this pin and the resulting voltage is measured. the two tables below provide the resistor values for each corresponding svid address. for dual addressing follow the dual svid address table. the address value is latched at start ? up. if vboota is pulled to vcc the aux rail will be removed from the svid bus, the address will then follow the single address svid table below. table 4. dual svid address table resistor value main rail svid address aux rail svid address 10k 0000 0001 25k 0010 0011 45k 0100 0101 70k 0110 0111 95k 1000 1001 125k 1010 1011 165k 1100 1101 table 5. single svid address table resistor value main rail svid address (vboota tied to vcc) 10k 0000 22k 0001 36k 0010 51k 0011 68k 0100 91k 0101 120k 0110 160k 0111 220k 1000 remote sense amplifier a high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage to this signal then goes through a standard error compensation network and into the inverting input of the error amplifier. the non ? inverting input of the error amplifier is connected to the same 1.3 v reference used for the differential sense amplifier output bias. v difout v vsp v vsn 1.3 v v dac (eq. 1) v droop v csref high performance voltage error amplifier a high performance error amplifier is provided for high bandwidth transient performance. a standard type 3 compensation circuit is normally used to compensate the system. differential current feedback amplifiers each phase has a low offset differential amplifier to sense that phase current for current balance. the inputs to the csnx and cspx pins are high impedance inputs. it is recommended that any external filter resistor rcsn not exceed 10 k to avoid offset issues with leakage current. it is also recommended that the voltage sense element be no less than 0.5 m for accurate current balance. fine tuning of this time constant is generally not required.
ncp6121 http://onsemi.com 22 ccsn rcsn dcr lphase 1 2 swnx vout cspx csnx r csn l phase c csn * dcr figure 6. the individual phase current is summed into to the pwm comparator feedback in this way current is balanced is via a current mode control approach. total current sense amplifier the ncp6121 uses a patented approach to sum the phase currents into a single temperature compensated total current signal. this signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. the total current signal is floating with respect to csref. the current signal is the difference between cscomp and csref. the ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. the amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (dcr). rth is placed near an inductor to sense the temperature of the inductor. this allows the filter time constant and gain to be a function of the rth ntc resistor and compensate for the change in the dcr with temperature. figure 7. the dc gain equation for the current sensing: v cscomp ? csref ? rcs2 rcs1*rth rcs1 rth rph * i outtotal * dcr (eq. 2) set the gain by adjusting the value of the rph resistors. the dc gain should set to the output voltage droop. if the voltage from cscomp to csref is less than 100 mv at iccmax then it is recommend to increase the gain of the cscomp amp and add a resister divider to the droop pin filter. this is required to provide a good current signal to offset voltage ratio for the ilimit pin. when no droop is needed, the gain of the amplifier should be set to provide ~100 mv across the current limit programming resistor at full load. the values of rcs1 and rcs2 are set based on the 100k ntc and the temperature effect of the inductor and should not need to be changed. the ntc should be placed near the closest inductor. the output voltage droop should be set with the droop filter divider. the pole frequency in the cscomp filter should be set equal to the zero from the output inductor. this allows the circuit to recover the inductor dcr voltage drop current signal. ccs1 and ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. it is best to fine tune this filter during transient testing. f z dcr@25 c 2*pi*l phase (eq. 3) f p 1 2 * pi * rcs1 rcs1*rth@25 c rcs1 rth@25 c * ( ccs1 ccs2 ) (eq. 4) programming the current limit the current limit thresholds are programmed with a resistor between the ilimit and cscomp pins. the ilimit pin mirrors the voltage at the csref pin and mirrors the sink current internally to iout (reduced by the iout current gain) and the current limit comparators. the 100% current limit trips if the ilimit sink current exceeds 10 a for 50 s. the 150% current limit trips with minimal delay if the ilimit sink current exceeds 15 a. set the value of the current limit resistor based on the cscomp ? csref voltage as shown below. r limit rcs2 rcs1*rth rcs1 rth rph * iout limit * dcr 10 (eq. 5) or r limit limit v cscompudahscsref@ilimit 10 (eq. 6) programming droop and dac feed ? forward filter the signals droop and csref are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. the total current feedback should be filtered before it is applied to the droop pin. this filter impedance provides dac feed ? forward during dynamic vid changes. programming this filter can be made simpler if cscomp ? csref is equal to the droop voltage. rdroop sets the gain of the dac feed ? forward and cdroop provides the time constant to cancel the time constant of the system per the following
ncp6121 http://onsemi.com 23 equations. c out is the total output capacitance and rout is the output impedance of the system. + ? 5 7 6 csref cscomp cssum cdroop rdroop droop rdroop cout * rout * 453.6 10 6 cdroop r out *c out rdroop figure 8. if the droop at maximum load is less than 100mv at iccmax we recommend altering this filter into a voltage divider such that a larger signal can be provided to the ilimit resistor by increasing the cscomp amp gain for better current monitor accuracy. the droop pin divider gain should be set to provide a voltage from droop to csref equal to the amount of voltage droop desired in the output. a current is applied to the droop pin during dynamic vid. in this case rdroop1 in parallel with rdroop2 should be equal to rdroop. + ? 5 7 6 csref cssum cscomp cdroop rdroop1 droop rdroop2 figure 9. programming iout the iout pin sources a current in proportion to the ilimit sink current. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull ? up resistor from 5 v v cc can be used to offset the iout signal positive if needed. r iout 2.0 v * r limit 10 * rcs2 rcs1*rth rcs1 rth rph * iout icc_max * dcr (eq. 7) programming icc_max and icc_maxa the svid interface provides the platform icc_max value at register 21h for both the multiphase and the single phase rail. a resistor to ground on the imax and imaxa pins program these registers at the time the part in enabled. 10 a is sourced from these pins to generate a voltage on the program resistor. the value of the register is 1 a per lsb and is set by the equation below. the resistor value should be no less than 10k. icc_max 21h r*10 a * 256 a 2v (eq. 8) programming tsense and tsensea two temperature sense inputs are provided. a precision current is sourced out the output of the tsense and tsensea pins to generate a voltage on the temperature sense network. the voltages on the temperature sense inputs are sampled by the internal a/d converter. a 100k ntc similar to the vishay ert ? j1vs104ja should be used. rcomp1 is mainly used for noise. see the specification table for the thermal sensing voltage thresholds and source current. rcomp2 8.2k rntc 100k cfilter 0.1uf agnd agnd rcomp1 0.0 tsense figure 10. precision oscillator a programmable precision oscillator is provided. the clock oscillator serves as the master clock to the ramp generator circuit. this oscillator is programmed by a resistor to ground on the rosc pin. the oscillator frequency range is between 200 khz/phase to 1 mhz/phase. the rosc pin provides approximately 2 v out and the source current is mirrored into the internal ramp oscillator. the oscillator frequency is approximately proportional to the current flowing in the rosc resistor. ncp6121 operating frequency versus r osc 6.98 k 400 khz fs r osc (eq. 9)
ncp6121 http://onsemi.com 24 the oscillator generates triangle ramps that are 0.5 ~ 2.5 v in amplitude depending on the vrmp pin voltage to provide input voltage feed forward compensation. the ramps are equally spaced out of phase with respect to each other and the signal phase rail is set half way between phases 1 and 2 of the multi phase rail for minimum input ripple current. programming the ramp feed ? forward circuit the ramp generator circuit provides the ramp used by the pwm comparators. the ramp generator provides voltage feed ? forward control by varying the ramp magnitude with respect to the vrmp pin voltage. the vrmp pin also has a 4 v uvlo function. the vrmp uvlo is only active after the controller is enabled. the vrmp pin is high impedance input when the controller is disabled. the pwm ramp time is changed according to the following, v ramppk pk pp 0.1 * v vrmp (eq. 10) vin comp ? il duty vramp _pp figure 11. programming trbst the trbst pin provides a signal to offset the output after load release overshoot. this network should be fine tuned during the board tuning process and is only necessary in systems with significant load release overshoot. the trbst network allows maximum boost for low frequency load release events to minimize load release undershoot. the network time constants are set up to provide a trbst roll of at higher frequencies where it is not needed. cboost1 * rbst1 controls the time constant of the load release boost. this should be set to counter the under shoot after load release. rbst1 + rbst2 controls the maximum amount of boost during rapid step loading. rbst2 is generally much larger then rbst1. the cboost2 * rbst2 time constant controls the roll off frequency of the trbst function. rbst2 cboost1 rbst1 cboost2 rbst3 fb trbst figure 12. pwm comparators during steady state operation, the duty cycle is centered on the valley of the triangle ramp waveform and both edges of the pwm signal are modulated. during a transient event the duty will increase rapidly and proportionally turning on all phases as the error amp signal increases with respect to the ramps to provide a highly linear and proportional response to the step load. phase detection sequence during start ? up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the pwm outputs. normally, ncp6121 operates as a 3 ? phase vcore + 1 ? phase vaux pwm controller. connecting pwm2 pin to v cc programs 2 ? phase operation. the aux rail can be disabled by pulling the vboota signal to v cc . this changes the svid address scheme to allow the multiphase to be programmed to any svid address odd or even. see the register resistor programming table. table 6. phase count table ? ncp6121 number of phases ncp6121 3+1 pwm2 connected, vboota pro- grammed 2+1 pwm2 tied to vcc, vboota pro- grammed 3+0 pwm2 connected, vboota tied to vcc 2+0 pwm2 tied to vcc, vboota tied to vcc
ncp6121 http://onsemi.com 25 table 7. 2+1 unused pin connection table ? ncp6121 unused pin connect to pwm2 vcc csn2 gnd or vcc csp2 same as csn2 table 8. 3+0 unused pin connection table ? ncp6121 unused pin connect to vboota vcc vspa gnd vsna gnd diffouta float fba compa compa fba trbsta float cspa gnd csna gnd cscompa cssuma cssuma cscompa droopa gnd or cscompa ilima float iouta gnd tsensea gnd pwma float table 9. 2+0 unused pin connection table ? ncp6121 unused pin connect to pwm2 vcc csn2 gnd or vcc csp2 same as csn2 vboota vcc vspa gnd vsna gnd diffouta float fba compa compa fba trbsta float cspa gnd csna gnd cscompa cssuma cssuma cscompa droopa gnd or cscompa ilima float iouta gnd tsensea gnd pwma float protection features input under voltage protection ncp6121 monitors the 5 v v cc supply and the vrmp pin for under voltage protection. the gate driver monitors both the gate driver v cc and the bst voltage (12 v drivers only). when the voltage on the gate driver is insufficient it will pull drvon low and notify the controller the power is not ready. the gate driver will hold drvon low for a minimum period of time to allow the controller to restart its start ? up sequence. in this case the pwm is set back to the mid state and soft start would begin again. see the figure below. dac gate driver pulls drvon low during driver uvlo and calibration if drvon is pulled low the controller will hold off its startup figure 13. gate driver uvlo restart
ncp6121 http://onsemi.com 26 soft ? start soft ? start is implemented internally. a digital counter steps the dac up from zero to the target voltage based on the predetermined s lew rate in the spec table. for ncp6121, the pwm signals will start out open with a test current to collect data on phase count and for setting internal registers. after the configuration data is collected the controller enables and sets the pwm signal to the 2.0 v mid state to indicate that the drivers should be in diode mode. drvon will then be asserted and the comp pin released to begin soft ? start. the dac will ramp from zero to the target dac codes and the pwm outputs will begin to fire. each phase will move out of the mid state when the first pwm pulse is produced preventing the discharge of a pre ? charged output. figure 14. soft ? start sequence over current latch ? off protection during normal operation a programmable total current limit is provided that scales with the phase count during power saving operation. the level of total current limit is set with the resistor from the ilim pin to cscomp. the current through the external resistor connected between ilim and cscomp is then compared to the internal current of 10 a and 15 a. if the current into the ilim pin exceeds the 10 a level an internal latch ? off counter starts. the controller shuts down if the fault is not removed after 50 s. if the current into the pin exceeds 15 a the controller will shut down immediately. to recover from an ocp fault the en pin must be cycled low. the over ? current limit is programmed by a resistor on the ilim pin. the resistor value can be calculated by the following equation: r ilim v cscomp v csref 10 a (eq. 11) under voltage monitor the output voltage is monitored at the output of the differential amplifier for uvlo. if the output falls more than 300 mv below the dac ? droop voltage the uvlo comparator will trip sending the vr_rdy signal low. over voltage protection during normal operation the output voltage is monitored at the differential inputs vsp and vsn. if the output voltage exceeds the dac voltage by ap proximately 175 mv, pwms will be forced low until the voltage drops below the ovp threshold after the first ovp trip the dac will ramp down to zero to avoid a negative output voltage spike during shutdown. when the dac gets to zero the pwms will be forced low and the drvon will remain high. to reset the part the enable pin must be cycled low. during soft ? start, the ovp threshold is set to 2.2 v. this allows the controller to start up without false triggering the ovp. prior to soft ? start the gate drivers will provide ovp protection directly at the switching nodes. dac vsp_vsn ovp threshold latch off ovp triggered pwm figure 15. ovp threshold behavior layout notes the ncp6121 has differential voltage and current monitoring. this improves signal integrity and reduces noise issues related to layout for easy design use. to insure proper function there are some general rules to follow. always place the inductor current sense rc filters as close to the csn and csp pins on the controller as possible. place the v cc decoupling cap as close as possible to the controller vcc pin, the resistor in series should always be no higher than 2.2 to avoid large voltage drop. the high frequency filter cap on csref and the 10 csref resistors should be placed close to the controller. the small high feed back cap from comp to fb should be as close to the controller as possible. please minimize the capacitance to ground of the fb traces by keeping them short. the filter cap from cscomp to csref should also be close to the controller.
ncp6121 http://onsemi.com 27 ordering information device package shipping ? NCP6121S52MNR2G qfn52 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp6121 http://onsemi.com 28 package dimensions qfn52 6x6, 0.4p case 485be issue b seating note 4 k 0.10 c (a3) a a1 d2 b 1 14 27 52 e2 52x l bottom view detail c top view side view d a b e 0.10 c pin one location 0.10 c 0.08 c c 40 e a 0.07 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.60 4.80 e 6.00 bsc 4.80 e2 4.60 e 0.40 bsc l 0.25 0.45 l1 0.00 0.15 note 3 plane dimensions: millimeters 0.25 4.80 0.40 4.80 52x 0.63 52x 6.40 6.40 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* detail b l1 detail a l alternate terminal constructions l 0.30 ref pitch 52x pkg outline l2 0.15 ref l2 detail c 8 places l2 detail a detail d 8 places 0.11 0.49 detail d on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp6121/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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